Local oxidation of silicon (LOCOS) is the most commonly used isolation technology for silicon integrated circuits. Unfortunately, LOCOS has an inherently large field oxide encroachment that precludes it from being used in advanced integrated circuits requiring high device packing densities. In a standard LOCOS process a thin layer of pad oxide is thermally grown on the surface of a silicon wafer. A silicon nitride layer is then deposited onto the pad oxide layer. The silicon nitride layer is then photolithographically patterned and etched to define active regions and isolation regions. Field oxide is then grown in the isolation regions while the active regions, which are masked by the patterned silicon nitride layer, are protected from the oxidation process. After field oxide growth, however, the area of the resulting active region is smaller than the actual intended area, as defined by the patterned silicon nitride layer. This occurs because oxygen laterally diffuses through the pad oxide layer, underneath the patterned silicon nitride mask, and reacts with the underlying silicon surface. Therefore, field oxide is formed not only in the isolation regions, but it also encroaches into the adjacent active regions. As a result, scaling of active area dimensions is limited and therefore integrated circuits with high device packing densities cannot be achieved with standard LOCOS isolation.
In order to reduce field oxide encroachment, several LOCOS-like isolation techniques have been proposed. In one approach the pad oxide layer lying underneath the silicon nitride oxidation mask is undercut to form a cavity. The cavity is then filled using a conformal layer of polysilicon. During field oxidation, the polysilicon filled cavity acts as a diffusion barrier and thus inhibits the transportation of oxygen to the silicon surface underlying the edge of the silicon nitride oxidation mask. Unfortunately, the polysilicon filled cavity is not a perfect diffusion barrier. Therefore, oxidation of the silicon surface underlying the edge portion of the oxidation mask still occurs, and as a result, active regions are still encroached upon by the field oxide.
In a second approach, the cavity is filled with a conformal layer of silicon nitride, which is then anisotropically etched to form a sidewall spacer adjacent to the silicon nitride filled cavity. During field oxide formation, the silicon nitride filled cavity and the silicon nitride sidewall spacer both act as diffusion barriers and thus inhibit the transportation of oxygen to the silicon surface, which is underlying the edge portion of the oxidation mask. Unfortunately, with this approach, it is difficult to uniformly control field oxide encroachment. The sidewall spacer formation process requires that silicon nitride be selectively etched with respect to the underlying oxidation mask. Silicon nitride, however, is predominantly used as the oxidation mask in these isolation schemes. Therefore, as a result of variations in the silicon nitride etch rate and in spacer film thickness, the silicon nitride oxidation mask is non-uniformly etched and has a thickness that varies across the wafer and from wafer to wafer. Since field oxide encroachment is highly dependent on oxidation mask thickness, the resulting encroachment into active regions also varies across the wafer, and from wafer to wafer. Additionally, the sidewall spacer formation process also reduces the geometry of the isolation regions. Therefore, field oxide thinning, which is known to occur in isolation regions which have a small geometry, is further exacerbated by the presence of the silicon nitride sidewall spacers. Therefore, with this isolation technique, device scaling is further limited by field oxide thinning. Accordingly, a need exists for an isolation process that effectively and reproducibly reduces field oxide encroachment and minimizes field oxide thinning.